Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

• A) Reset
• B) Latch
• C) Toggle
• D) Set

The Test Vector definition defines the test vectors for all the three counter inputs and _______counter output/outputs.

• A) Two
• B) Four
• C) One
• D) Three

Asynchronous mean that_____________

• A) Each flip-flop is enabled by the output of the preceding flip-flop
• B) Each alternative flip-flop after the first one is enabled by the output of the preceding flip-flop
• C) Each flip-flop except the last one is enabled by the output of the preceding flip-flop
• D) Each flip-flop after the first one is enabled by the output of the preceding flip-flop

The _____________ description is used to simulate the logic circuit and verify its operation.

• A) Test file
• B) Logic
• C) Test vector
• D) Declaration

+ is written in ABEL as__________ .

• A) !
• B) @
• C) $
• D) #

Demultiplexer is also called _________

• A) Data router
• B) Data distributor
• C) Data selector
• D) Data encoder

In Combinational Output with feedback to AND array, the active-state of the output is determined by the _________ input.

• A) OR
• B) NOT
• C) XOR
• D) AND

If S=1 and R=0, then for positive edge triggered flip-flop
Q(t+1) = _________

• A) Invalid
• B) 0
• C) Input is invalid
• D) 1

The S-R latch has two inputs, therefore _________ different combinations of inputs can be applied to control the operation of the S-R latch.

• A) eight
• B) sixteen
• C) two
• D) four

Which mechanism allocate the binary values to the states in order to reduce the cost of the combinational circuits?

• A) State Reduction
• B) State Minimization
• C) State Evaluation
• D) State Assignment

Choose the best possible answer of following question:
The D flip-flop is only activated by____________.

• A) both positive & negative edge trigger
• B) a negative edge trigger
• C) a positive edge trigger
• D) None of the given options

With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in

• A) 10 micro seconds
• B) 80 micro seconds
• C) 8 micro seconds
• D) 80 mili seconds

In gated SR latch, what is the value of the output if EN=1, S=1 and R=0?

• A) 0
• B) Qt
• C) Invalid
• D) 1

A __________ attached to the Select inputs of the Demultiplexer routes the incoming serial bits to successive outputs where each bit is stored.

• A) memory
• B) counter
• C) buffer
• D) data

A 4-bit binary UP/DOWN counter is in the binary state zero. the next state in the DOWN mode is_____________

• A) 1111
• B) 1000
• C) 1110
• D) 0001

Once the state diagram is drawn for any sequential circuit the next step is to draw

• A) Next-state table
• B) Karnaugh map
• C) Logic expression
• D) Transiation table

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.

• A) XOR
• B) AND
• C) OR
• D) NOT

A-stable multi-vibrator continuously changes from one unstable state to the other without any_______.

• A) External trigger
• B) Output
• C) Flip flop
• D) Variable

There are _____________ possible combinations of the Simple Mode in which OLMC can be configured.

• A) three
• B) four
• C) five
• D) two

Divide-by-32 counter can be acheived by using

• A) DIV 16 and DIV 32
• B) Flip-Flop and DIV 32
• C) Flip-Flop and DIV 10
• D) Flip-Flop and DIV 16