The ABEL symbol for “OR” operation is

• A) &
• B) !
• C) $
• D) #

Two states are said to be equal if they have exactly same______.

• A) Outputs
• B) Inputs
• C) None of the given options
• D) Next state

Three cascaded modulus-10 counters have an overall modulus of

• A) 100
• B) 10000
• C) 30
• D) 1000

Flip flops are also called _____________

• A) Bi-stable transformer
• B) Bi-stable multivibrators
• C) Bi-stable dualvibrators
• D) Bi-stable singlevibrators

The duration for which the elevator doors are opened, and remain open, and time it takes for the elevator to move from one floor to the next can be determined by a/an__________.

• A) Clock Signal
• B) None of the given options
• C) Input Signal
• D) Output Signal

In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is ____________

• A) 0000
• B) 0001
• C) 10000
• D) 1111

In asynchronous digital systems all the circuits change their state with respect to a common clock

• A) False
• B) True
• C)
• D)

In synchronous digital circuits the ______of one flip-flop is connected to the ______of a second flip-flop.

• A) Output, input
• B) Clock signal, Output
• C) Input, Output
• D) Input, clock signal

Select the mode of programming in which GAL16V8 can be programmed.

• A) Registered Mode
• B) All of the given options
• C) Simple Mode
• D) Complex Mode

A Divide-by-20 counter can be acheived by using

• A) Flip-Flop and DIV 32
• B) Flip-Flop and DIV 10
• C) Div 10 and DIV 16
• D) Flip-Flop and DIV 16

When an eight bit serial in/out shift register is used for a 24 micro seconds time delay, the clock frequency must be

• A) 8 MHz
• B) 333 KHz
• C) 41.67 KHz
• D) 125 KHz

The 3-bit up counter can be implemented using ________ flip-flop(s).

• A) S-R Flip-flips and D-Flip-flops
• B) S-R Flip-flops Only
• C) S-R Flip-flops or D-Flip-flops
• D) D-Flip-flop Only

Combinational Logic is used for combinational circuits, where as Registered Logic is based on _____________ circuits.

• A) Multiple
• B) Consecutive
• C) Single
• D) Sequential

The____________ output has the output of the OR gate connected through an XOR gate to the tri-state buffer.

• A) PLA
• B) Programmed Polarity
• C) Combinational input/
• D) Combinational

A NOR based S-R latches maintain the output state when both the set and reset inputs are _____________.

• A) invalid
• B) active
• C) inactive
• D) consistent

The terminal count of a 4-bit binary counter in the DOWN mode is____________

• A) 0000
• B) 1111
• C) 1100
• D) 0011

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

• A) The clock pulse is HIGH
• B) The clock pulse is LOW
• C) The clock pulse transition from HIGH to LOW
• D) The clock pulse transition from LOW to HIGH

when the transmission line is idle in an asynchronous transmission

• A) State of transmission line is not used to start transmission
• B) It is set to logic high
• C) It is set to logic low
• D) It remains in previous state

In 1-to-4 demultiplexer, how many select lines are required

• A) 5
• B) 2
• C) 4
• D) 3

A positive edge-triggered flip-flop changes its state when ________________

• A) High-to-low transition of clock
• B) Low-to-high transition of clock
• C) Preset input (PRE) is set
• D) Enable input (EN) is set