The OLMC of the GAL16V8 is similar to the OLMC of the ______________ with some enhancements.

• A) GAL22V10
• B) GAL16V10
• C) GAL12V10
• D) GAL14V10

A-stable multi-vibrator is an Oscillator which does not have any__________.

• A) Output
• B) Stable state
• C) Flip flop
• D) Unstable state

The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________ inputs.

• A) Asynchronous
• B) Sequential
• C) Synchronous
• D) Combinational

The term hold always means _______.

• A) Q=1, Q ̅=0
• B) Q=0, Q ̅=0
• C) Q=0, Q ̅=1
• D) No change

The _____ inputs can be directly mapped to Karnaugh maps.

• A) Flip-flop
• B) S-R
• C) External
• D) J-K

The characteristic equation of D-flip-flop implies that _____.

• A) The next state is dependent on previous state
• B) The next state is independent of inputs
• C) The next state is independent of present state
• D) The next state is dependent on present state

Each stage of Master-slave flip-flop works at ____ of the clock signal

• A) One fourth
• B) One third
• C) Each stage works on complete clock signal
• D) One half

The 74HC163 is a 4-bit Synchronous Counter.it has..............data output pins

• A) 4
• B) 2
• C) 6
• D) 8

A transparent mode means _____________

• A) Input Hold time is zero (no need to maintain input after clock transition)
• B) The changes in the data at the inputs of the latch are seen at the output
• C) Propagation Delay is zero (Output is immediately changed when clock signal is applied)
• D) The changes in the data at the inputs of the latch are not seen at the output

A standard interface for programming the In-System PLD consists of

• A) 8-wire
• B) 16-wire
• C) 2-wire
• D) 4-wire

The terminal count of a 4-bit binary counter in the UP mode is____________

• A) 0011
• B) 1111
• C) 1100
• D) 0000

An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________

• A) Q output of all flip-flops to J input of next flip-flops
• B) Q’ output of all flip-flops to clock input of next flip-flops
• C) Q’ output of all flip-flops to K input of next flip-flops
• D) Q output of all flip-flops to clock input of next flip-flops

The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)

• A) (2 raise to power n)
• B) (2 raise to power n and then minus 1)
• C) (n raise to power 2 and then minus 1)
• D) (n raise to power 2)

Karnaugh map is used in designing

• A) a clock
• B) a counter
• C) an UP/DOWN counter
• D) All of the above

___________ is one of the examples of asynchronous inputs.

• A) J-K input
• B) Clear Input (CLR)
• C) S-R input
• D) D input

________ flip-flops are obsolete now.

• A) Master-Slave
• B) D-Flipflop
• C) T-Flipflop
• D) Edge-triggered

The absence of a ________________ element in sequential circuit restricts the use of digital combinational circuits to certain application areas.

• A) memory
• B) cell
• C) clock
• D) device

A divide-by-10 ring counter requires a minimum of

• A) ten flip-flops
• B) five flip-flops
• C) four flip-flops
• D) twelve flip-flops

An Astable multivibrator is known as a(n) _______

• A) Dual-shot
• B) Oscillator
• C) One-shot
• D) Booster

In designing any synchronous counter a modulus number is used which determine the number of............ used in a counter

• A) Counters
• B) Registers
• C) Flip Flops
• D) Latches