_____ form the branch control field in the micro instruction.

• A) A Bits
• B) B Bits
• C) M Bits
• D) C Bits

Which of the following control signals is NOT activated during instruction fetch operation?

• A) LC
• B) PCout
• C) Cout
• D) LMAR

The __________ instruction is completed once memory access has been made and the memory location has been written to.

• A) Branch
• B) Store
• C) Control
• D) Link

A collection of -----------is called a micro program.

• A) Registers
• B) large scale operations
• C) Microinstructions
• D) DMA

Every time you press a key, an interrupt is generated.
This is an example of

• A) Hardware interrupt
• B) All of the given
• C) Software interrupt
• D) None of the given

_____________ is said to occur when a 0 is received instead of a stop bit.

• A) Framing Error
• B) Parity Error
• C) Block Error
• D) Over-run Error

Which of the following is not True regarding serial communication?

• A) Inefficient
• B) Slow
• C) Easy to implement
• D) High Cost

Which one of the following is NOT a technique used when the CPU wants to exchange data with a peripheral device?

• A) Interrupt driven I/O
• B) Programmed I/O
• C) Virtual Memory
• D) Direct Memory Access (DMA)

In which one of the following methods for resolving the priority, the device with the highest priority is placed in the first position, followed by lower-priority devices up to the device with the lowest priority, which is placed last in the series?

• A) Parallel
• B) Asynchronous
• C) Semi-synchronous
• D) Daisy-Chaining Priority

________ controls the sequence of the flow of microinstructions.

• A) Virtual Memory
• B) DMA Controller
• C) Multiplexer
• D) Micro program controller

Below given RTL description belongs to which stage of pipe-lining?

IR2 ← M [PC];
PC2 ← PC+4;

• A) ALU Operation
• B) Instruction Fetch
• C) Memory Access
• D) Instruction Decode

Identify the type of serial communication error condition in which "0" is received instead of a stop bit (which is always a "1")?

• A) Under-run error
• B) Parity error
• C) Overrun error
• D) Framing error

__________ means that the CPU should input data from an input device only when the device is ready to provide data and send data to an output device only when it is ready to receive data.

• A) Asynchronous transmission
• B) Data location
• C) Data transfer
• D) Data synchronization

A computer interface is an ___________ circuit that matches the requirements of the two subsystems between which it is connected

• A) Electronic
• B) Obituary
• C) Primary
• D) Digital

What is the status of the ACKNLG# signal when a character is completely received by the printer?

• A) It remains unaffected
• B) It goes from high to low
• C) It toggles its state
• D) It goes from low to high

_________ is a technique in which some of the CPU’s address lines forming an input to the address decoder are ignored.

• A) Microprogramming
• B) Pipelining
• C) Instruction pre-fetching
• D) Partial decoding

______________ usually involves calculating the target address and evaluating a condition.

• A) Load/Store instructions
• B) ALU instructions
• C) Pipelined SRC
• D) Branch Instructions

_____ form the branch address field in the micro instruction.

• A) A Bits
• B) B Bits
• C) C Bits
• D) M Bits

A software routine performed when an interrupt is received by the computer is called as ---------

• A) Trap
• B) Interrupt
• C) Exception
• D) Interrupt handler

_________ hazard occurs when attempting to access the same resource in different ways at the same time

• A) Structural
• B) Branch
• C) Data
• D) Instruction