In Master-Slave flip-flop setup, the master flip flop operates at __________

• A) Master-Slave flip-flop does not operate on pulses, rather it is edge triggered.
• B) Both Master-Slave operate simultaneously
• C) Positive half cycle of pulse
• D) Negative half cycle of pulse

____________ is said to occur when multiple internal variables change due to change in one input variable

• A) Hold delay
• B) Clock Skew
• C) Hold and Wait
• D) Race condition

When the fuse of the _________ gate input is blown to set the input to logic high, the output of the XOR gate is opposite of the OR gate output.

• A) XOR
• B) NAND
• C) AND
• D) OR

In gated SR latch, what is the value of the output if EN=1, S=0 and R=0?

• A) Qt
• B) Invalid
• C) 0
• D) 1

The power consumed by a flip-flop is defined by _____________

• A) P = Vcc x Icc
• B) P = Vcc x Rcc
• C) P = Icc x Rcc
• D) P = Mcc x Vcc

To parallel load a byte of data into a shift register, there must be

• A) one clock pulse for each 1 in the data
• B) eight clock pulse
• C) one clock pulse
• D) one clock pulse for each 0 in the data

Number of states in an 8-bit Johnson counter sequence are:

• A) 16
• B) 8
• C) 12
• D) 14

A negative edge-triggered flip-flop changes its state when ________________

• A) Preset input (PRE) is set
• B) High-to-low transition of clock
• C) Low-to-high transition of clock
• D) Enable input (EN) is set

A flip-flop is presently in SET state and must remain SET on the next clock pulse. What must j and K be?

• A) J = 1, K = X(Don't care)
• B) J = 1, K = 0
• C) J = X(Don't care), K = 0
• D) J = 0, K = X(Don't care)

To serially shift a byte of data into a shift register, there must be

• A) one clock pulse for each 1 in the data
• B) eight clock pulses
• C) one clock pulse
• D) one load pulse

If S=1 and R=1, for negative edge triggered flip-flop then
Q(t+1) = _________

• A) 0
• B) Input is invalid
• C) 1
• D) Invalid

______________________are implemented by combining combinational circuits with memory elements.

• A) PLDs
• B) PLA
• C) system
• D) Sequential circuits

The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the ___________

• A) Hold time
• B) Set-up time
• C) Pulse Stability time (PST)
• D) Pulse Interval time

RCO stands for __________

• A) Reconfiguration Clock Output
• B) Ripple Counter Output
• C) Ripple Clock Output
• D) Reconfiguration Counter Output

A Quad 1-of-4 MUX has four Multiplexers, each multiplexer has_____ inputs and a single output.

• A) Four
• B) Eight
• C) Five
• D) Six

A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?

• A) 1011
• B) 0011
• C) 1001
• D) 1100

GAL can be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to connect a _________ with a __________.

• A) row,row
• B) column,column
• C) column,row
• D) row,column

In Master-Slave flip-flop the Clock signal is connected to Slave flip-flip using ________ gate

• A) NOT
• B) AND
• C) OR
• D) NAND

Tri-State Buffer is a __________ gate with a control line that disconnects the output from the input.

• A) NAND
• B) AND
• C) OR
• D) NOT

We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), to supply the required frequency to each part of circuit, we can get help by using ___________

• A) D-flipflop
• B) Using S-R Flop-Flop
• C) T-Flip-Flop
• D) J-K flip-flop