The outputs of SR latches in elevator state machine are generated by combinational circuits therefore, these outputs are defined as ISTYPE ‘________’.

• A) com.buffer
• B) com.org
• C) com.reg
• D) reg.buffer

The bit capacity of a memory that has 1024 addresses and can store 8 bits at each address is:

• A) 4096
• B) 8
• C) 8192
• D) 1024

You have to choose suitable option when your timer will reset by considering this given code:
TRSTATE.CLK = clk;
TMRST: = (TRSTATE = = NSY2) # (TRSTATE = = EWY2);

• A) NSSR or TMRST
• B) EWRed or EWYel
• C) EWSR or NSRED
• D) NSY2 or EWY2

A complete unit of information is sometimes called a _______.

• A) Byte
• B) Nibble
• C) Word
• D) Bit

A 32-bit data word consists of:

• A) 2 bytes
• B) 2 nibbles
• C) 4 bytes
• D) 4 nibbles

Two State variables allow a maximum of ______ states.

• A) Four
• B) Two
• C) Eight
• D) Sixteen

Which of the following is a volatile memory?

• A) EPROM
• B) EEPROM
• C) PROM
• D) DRAM

The 64-cell array organized as 8 x 8 cell array is considered

• A) as an 64 byte memory
• B) as a 16 byte memory
• C) as an 8 byte memory
• D) as an 4 byte memory

The outputs of SR latches in elevator state machine are feed back to the _____ gate array for connection to the D-flipflops.

• A) AND
• B) XOR
• C) OR
• D) NOT

Which one flip-flop has an invalid output state?

• A) T
• B) D
• C) SR
• D) JK

_________ Yellow signal controlling the traffic on the East-West section.

• A) NSYel
• B) EWRed
• C) EWYel
• D) NSGrn

A negative edge-triggered flip-flop changes its state when ________________

• A) Enable input (EN) is set
• B) High-to-low transition of clock
• C) Low-to-high transition of clock
• D) Preset input (PRE) is set