Which one of the following methods for resolving the priority makes use of individual bits of a priority encoder?

• A) Asynchronous Priority
• B) Semi-synchronous Priority
• C) Parallel Priority
• D) Daisy-Chaining Priority

Which temporary register is loaded with either a register value from the register file or a constant from the instruction?

• A) X3
• B) Z4
• C) Y3
• D) Z5

In ________, a separate address space of the CPU is reserved for I/O operations.

• A) Isolated I/O
• B) Memory Mapped I/O
• C) None of above
• D) All of above

_______ signal has Output direction with respect to printer

• A) D<7..0>
• B) STROBE#
• C) INIT#
• D) ACKNLG#

ET = ___________.

• A) CPI / IC x T
• B) CPI x IC x T
• C) CP x IC x T
• D) CPI x IC / T

_______hazard occurs when an instruction attempts to access some data value that has not yet been updated by the previous instruction.

• A) Data
• B) Structural
• C) Instruction
• D) Branch

Tri-state buffers are used for removing ___________.

• A) Instruction contention
• B) Instruction collision
• C) bus contention
• D) bus collision

To set the value of micro-PC from branch address, the value of 4 to 1 multiplexer is ______________.

• A) 10
• B) 01
• C) 00
• D) 11

_____________ is/are example(s) of synchronous communication.

• A) Memory to Memory
• B) Register to Register
• C) Register to Memory
• D) All of the given

Which of the following pins of processor is designated for maskable interrupts?

• A) RINT
• B) NMI
• C) INTR
• D) MI

Connection to a CPU that provides a data path between the CPU and external devices, such as a keyboard, display, or reader is called-----------

• A) Buffer
• B) I/O port
• C) Memory mapping
• D) Processor

If a character is not available at the beginning of an interval, an ________ is said to occur.

• A) Parity Error
• B) Framing Error
• C) Overrun Error
• D) Under-run Error

Super-scalar processor divides the instructions into _________ classes.

• A) 4
• B) 3
• C) 5
• D) 2

Where does the processor store the address of the first instruction of the ISR?

• A) Interrupt handler
• B) Interrupt request
• C) Interrupt vector
• D) All of the given options

The third stage of the Pipelined version of SRC is;

• A) Memory access
• B) Register write
• C) ALU operation
• D) Instruction Fetch

_____ form the branch control field in the micro instruction.

• A) A Bits
• B) B Bits
• C) M Bits
• D) C Bits

Which of the following control signals is NOT activated during instruction fetch operation?

• A) LC
• B) PCout
• C) Cout
• D) LMAR

The __________ instruction is completed once memory access has been made and the memory location has been written to.

• A) Branch
• B) Store
• C) Control
• D) Link

A collection of -----------is called a micro program.

• A) Registers
• B) large scale operations
• C) Microinstructions
• D) DMA

Every time you press a key, an interrupt is generated.
This is an example of

• A) Hardware interrupt
• B) All of the given
• C) Software interrupt
• D) None of the given